Rcd 0: RcvHdr cnt 2048 entsize 32 dma_rtail ctrl 0x0000076d status 0x00000000, head 0 tail 0  sw head 0
Rcd 1: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000072d status 0x00000000, head 0 tail 0  sw head 0
Rcd 2: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000072d status 0x00000000, head 0 tail 0  sw head 0
Rcd 3: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000070d status 0x00000000, head 0 tail 0  sw head 0
Rcd 4: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000070d status 0x00000000, head 0 tail 0  sw head 0
Rcd 5: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000070d status 0x00000000, head 0 tail 0  sw head 0
Rcd 6: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000070d status 0x00000000, head 0 tail 0  sw head 0
Rcd 7: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000070d status 0x00000000, head 0 tail 0  sw head 0
Rcd 8: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000070d status 0x00000000, head 0 tail 0  sw head 0
Rcd 9: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000070d status 0x00000000, head 0 tail 0  sw head 0
Rcd 10: RcvHdr cnt 2048 entsize 32 nodma_rtail ctrl 0x0000070d status 0x00000000, head 0 tail 0  sw head 0
